1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to capacitor design, transistor design and cell isolation methods used to reduce the surface area occupied by a DRAM cell. More specifically, the present invention merges capacitor design, transistor design and cell isolation methods by using existing isolation trench sidewalls to form a DRAM capacitor and a access transistor thus significantly increasing DRAM cell density over currently fabricated DRAM cells.
2. Background Art
Various DRAM capacitor designs have been employed to reduce the surface area occupied by a single DRAM cell. Early DRAM designs employed flat horizontal capacitor plates. Later designs, intended to conserve chip surface area, employed trenches or fin structures to form narrow dimension capacitors with some vertical contribution to the capacitor plate surface area.
In addition to the shape and size of the capacitor plates, the type of cell isolation contributes to the overall DRAM cell size. Traditionally, field oxide produced by the Local Oxidation of Silicon process (LOCOS) was used as cell isolation. Unfortunately, a field oxide must cover a fairly wide area in order to effectively isolate adjacent cells. Further, it is difficult to control the growth of field oxide. Therefore, field oxide often occupies a significant amount of the chip surface area.
More recently, trench isolation has been employed. This involves etching a narrow isolation trench around the active areas (cells) on the chip. The isolation trenches are then filled with oxide or other dielectric to effectively isolate adjacent active areas from one another. While trench isolation requires more process steps than LOCOS isolation (field oxide), trench isolation can be made much narrower than LOCOS isolation. Therefore, DRAMs employing trench isolation can be packed more densely than DRAMs employing LOCOS isolation.
In addition to isolation regions and capacitors, access transistors can also occupy a significant amount of wafer surface which limits the DRAM cell density. Typically, the gate structure and the source region of the access transistor are formed on the semiconductor substrate surface. Forming a portion of the access transistor directly above the isolation trench would significantly reduce the area of semiconductor substrate required for a DRAM cell.
In the continuing quest for higher density DRAMs, improved structures employing narrow dimension trench isolation and access transistors are still needed.